RISC-V’s critics say openness did not prevent old mistakes
A detailed critique of RISC-V argues that its designers repeated problems computer architects already knew how to avoid. HN readers mostly accepted the trade-offs while resisting the verdict.
The RISC-V debate is not about whether an open instruction set is valuable. It is about whether the base specification makes the right compromises for cheap controllers and broad implementation.
HN’s reply was strikingly practical: even critics who recognize the flaws still prefer an open ISA to a future built only on proprietary ones.
An open ISA can still have awkward corners
The RISC-V critique argues that a modern instruction set should have learned more from earlier architectures. Its target is not a single chip but the design choices that become expensive when implementers repeat them at scale.
One commenter condensed the comparison to MIPS: the architecture can be forced into many roles, but that does not mean each choice is elegant. Another noted that a cheap microcontroller often exists mainly to configure surrounding custom hardware, which changes the priorities for its core.
"Better that there be an open ISA than them all be closed." — an HN commenter
That is the counterweight to the essay’s tone. Openness gives vendors and researchers room to improve, fork, and experiment even when the original design is imperfect.
Criticism becomes useful when hardware answers it
A commenter pointed to available RVA23 hardware, while another joked about a community-designed RISC-6. The valuable outcome is less a new label than a concrete question for implementers: which alleged weaknesses show up in silicon, tooling, and the low-cost devices RISC-V is supposed to serve?
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Law-enforcement hacking enters an AI-era arms race
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