IBM's '0.7nm' chip has nothing on it that measures 0.7nm

IBM says it broke the 1-nanometer barrier. The asterisk is in its own press release

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IBM's announcement leads with a superlative: the "world's first sub-1 nanometer chip technology." The centerpiece is nanostack, which IBM calls "the industry's first known three-dimensional, nanosheet-based design," an architecture that "vertically stacks and staggers transistors" to pack more of them into the same footprint. The headline figures: nearly 100 billion transistors on a fingernail-sized die, nearly twice the density of the 2nm chip IBM showed in 2021, and either 50% more performance or 70% greater energy efficiency, plus 40% scaling in SRAM.

The work runs out of IBM's research facility in Albany, New York, which is about to receive a High NA EUV (extreme ultraviolet) lithography tool from ASML, the printing technology IBM calls "essential for the future of logic scaling." IBM sees "a path to production in as early as the next 5 years."

The twist is that IBM tells on itself. Buried in the same release: "While transistor nodes now refer to a generation of manufacturing technology versus an exact physical dimension, IBM's 0.7 nm technology—also referred to as 7 angstroms—demonstrates how continued scaling remains possible." Translated: nothing on the chip is 0.7 nanometers. The node name and the ruler parted ways years ago.

The thread reads the fine print out loud

That caveat became the whole conversation on Hacker News. One commenter pulled the exact paragraph and translated the marketing into engineering:

"What they actually deliver is a 'nanostack architecture' built with ~5nm features that according to them is comparable to a hypothetical real sub-1nm chip… the name scales better than the tech." — an engineer parsing the release line by line

Another put the density-vs-dimension gap in one sentence:

"This doesn't mean that anything on the die actually measures 0.7nm — it means that it's roughly double the density as the previous node generation. At some point the industry decided to keep talking about 'nanometers' even though the actual transistor sizes have been decoupled from the node name for years." — a commenter on how process nodes are named

For readers new to the trick, a blunter version arrived:

"CPU nm marketing is a complete fabrication and the physical size of transistors has zero relation to the marketing claims. These are not, in fact, physically sub 1 nm, despite the bombastic claims." — a reader offering a primer for newcomers

The most authoritative voice didn't argue at all. He just linked his homework. Ian Cutress, the semiconductor analyst behind TechTechPotato and the More Than Moore newsletter, dropped his breakdown into the thread:

"For what it's worth, here's my 7000+ word deep dive into the technology." — Ian Cutress, semiconductor analyst

"Where do these chips actually go?"

Underneath the naming fight ran a second, more practical doubt: IBM keeps announcing silicon nobody seems to ship. "Keep hearing that IBM makes these incredible chips but don't see anyone using IBM chips," one reader asked. The answer is structural: IBM doesn't run leading-edge fabs anymore. A commenter spelled out what the 2026 announcement quietly omits:

"IBM debuts a PDK and some test structures, as they have no production fabs." — a commenter on what IBM actually shipped

And the history is sharper than "sold off." The deal went the other direction:

"Remember that IBM paid Global Foundries $1.5 billion to take their fabs and design services group. GF did not pay IBM. IBM paid GF to take the fabs away." — a reader recalling the 2014 GlobalFoundries deal

So the real product here isn't a chip you can buy. It's a process demo and a design kit, aimed at the partners who do own fabs: proof that scaling has a few more generations left, even if the generations are now named after a density target rather than a measurable line on the wafer. The achievement is real; the ruler on the box is not.